(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of depositing a boro-phosphate-silicate-glass (BPSG) layer and applying a dry air or dry N.sub.2 or dry Ar flow treatment.
(2) Description of the Prior Art
During the manufacturing of semiconductor devices numerous processing steps are taken to create device features such as interconnecting networks, isolation areas, passivation layers and electrode gate structures. During many of these processing steps an important aspect of the creation of a particular feature is the planarity of the surface that is created. Good planarity and the maintenance of good planarity is invariably a key aspect of many of the operations that are used to create a semiconductor device, this planarity can be enhanced or maintained as one of the aspects of a particular process or it can be a process in itself to create a surface with good planarity. Lack of planarity can cause, for instance, problems of depth of focus for the deposition of subsequent layers and problems of step coverage for the deposition of overlying interconnecting conductor lines. Lithographic processes used to create lines and other features of semiconductor devices require, especially in the micron and sub-micron device environment, the ability to establish and maintain sharp and well defined focus. Poor planarity also has a negative effect on required etching steps making it difficult to remove layers of equal thickness.
In maintaining or creating planarity, a planarization method can be of the subtractive type where material is removed from the surface in order to reduce the difference between high and low points within a plane. This removal can be based on mechanical or chemical removal of material. The disadvantage of the removal process is that this process, by its very nature, creates particles that are removed from the surface that is being planarized. These particles, if not completely removed from the environment, can lead to severe problems of surface contamination. Subsequent processing steps that occur at elevated temperatures may trap the contaminants having a serious negative impact on device performance and reliability. These contaminants can also lead to electrical shorts.
Another approach in creating or maintaining good surface planarity is to assure that dielectric layers have and maintain good planarity while the dielectric is being deposited. For this to be the case it is necessary to select dielectric materials and methods of creating the dielectric layer that lead to the desired planarity. Since dielectric layers can be placed at a variety of locations within the construction of a semiconductor device, this approach may lead to a large variety of dielectric materials and methods of dielectric deposition in order to address each of these different dielectric applications. For all of these applications the stated objective is the same, that is to form inter-level dielectrics that have good planarity while at the same time meeting the objective of providing separation and insulation between the layers that surround the dielectric, in many applications these layers are interconnecting conducting lines, bond pads or other levels of metal.
The latter approach of creating inherently planar surface frequently uses boro-phosphate-silicate-glass (BPSG) as a dielectric material. BPSG can be formed as a spin-on material that can be cured after it has been deposited on a surface. BPSG can also be formed within a Chemical Vapor Deposition (CVD) chamber, often used with a plasma enhanced or plasma assisted environment. By heating the deposited BPSG (after it has been deposited) to a temperature of about 900 degrees C., the BPSG can be made to reflow thereby creating a surface of good planarity.
The reflow process has a tendency to create surface imperfections in the form of grains in the surface of the created layer of BPSG. The boron and phosphorous in the BPSG react with oxygen and/or vapor in the surrounding air, the grains that are formed in this manner contain a large amount of phosphorous and oxygen. The chemical reactions proceed as follows:
B.sub.2 O.sub.3 +3H.sub.2 O{character pullout}2H.sub.3 BO.sub.3 PA1 P.sub.2 O.sub.5 +3H.sub.2 O{character pullout}2H.sub.3 PO.sub.4 PA1 H.sub.3 BO.sub.3 +H.sub.3 PO.sub.4 {character pullout}BPO.sub.4.3H.sub.2 O PA1 H.sub.3 BO.sub.3 +H.sub.3 PO.sub.4.fwdarw.BPO.sub.4 +3H.sub.2 O
The chemical reaction of flow is:
BPSG at a critical temperature range causes the phosphorous and the boron oxide to react with each other at the solid phase and to generate the precipitated grains. This prevents the BPSG from being flat. It is therefore of importance to prevent this formation of surface grains. Two distinct steps can be used to create a BPSG layer: first the BPSG is deposited, second the BPSG is heated so that the BPSG will flow and create good planarity. There is a time difference or lag between these two steps; this time difference may be in the order of several hours or more. It must also be noted at this time that, as shown in the above highlighted chemical reactions, an important contributor to the grain formation on the surface of the BPSG is the presence of H.sub.2 O with which the deposited BPSG comes in contact.
It is desirable to reduce the BPSG flow temperature because high temperatures result in excessive diffusion of junctions while metal oxide semiconductor gate oxides cannot be exposed to high temperature processing.
The flow of BPSG depends on film composition, flow temperatures, flow time and the flow ambient environment. The film composition can be altered by increasing for instance the boron concentration of 1 wt % in BPSG, this decreases the BPSG flow temperature by 40 degrees C. However, by increasing the phosphorous content by about 5 wt % in the BPSG, no further decrease in flow temperature is achieved. By further increasing the boron concentration of the BPSG film, this film becomes unstable and hyproscopic resulting in the requirement that the BPSG must be flowed immediately after it has been deposited.
BPSG further has the desirable property of acting as an alkali ion getter and of forming a low stress surface. Care must be taken that the doping limit of BPSG does not exceed certain limits since BPSG can in that case become the source of unwanted diffusion to the underlying silicon. It has been found that BPSG is primarily a source of phosphorous and that the phosphorous out-diffusion increases with increased level of boron.
BPSG is further used for sidewall contouring of contact holes by reflow. In addition to assuring that the contact holes are opened and that silicon-surface damage and contamination are minimized, it is also important to give the contact holes a shape that will result in good step coverage by the metal that is deposited into it. In general, better step coverage will be obtained if the walls of the openings are sloped and the top corners are rounded.
Several different approaches have been pursued to achieve these desired sidewalls profiles. One of the most popular is the reflow of the contact hole dielectric layer. Wafers are exposed to a high temperature step after the holes have been opened. This causes the CVD doped SiO.sub.2 layer to flow slightly, producing round corners and sloped sidewalls in the contact holes. BPSG flows at the relatively low temperature of about 900 degrees C. at atmospheric pressure.
From the above it is clear that BPSG is a dielectric material that has many desirable characteristics for its use as a dielectric. Grain formation in the surface of the deposited layer of BPSG must however be prevented while the flow temperature, where possible, must be held relatively low. The addition of boron or phosphorous to the BPSG offers some advantages in lowering the flow temperature of BPSG but these advantages are limited in scope. Defects on the surface of the deposited BPSG have been observed to appear between the lines of polysilicon and to appear after the flow of the BPSG. Changing boron or phosphorous in the BPSG concentration has only limited effect on the formation of irregularities in the surface of the deposited BPSG.
The preferred or target boron to phosphorous ratio in a BPSG film is B/P=2.1/5.1 wt %. This is the ideal condition of boron and phosphorous concentration to prevent the occurrence of BPSG surface irregularities but even under these conditions these irregularities are still observed. Typical ratio is B/P=2.4/5.4 wt %, this ratio is higher than the preferred ratio and the likelihood of surface defects is also higher.
A longer time lag between BPSG deposition and BPSG flow aggravates the problem of defect formation on the surface of the deposited layer of BPSG, for purposes of manufacturing throughput it is desirable to keep this lag time to less than 6 hours. There are however occasions within the manufacturing cycle where a considerable longer lag time is desirable, in some cases a lag time of days is of benefit.
Most of the BPSG surface defects have been observed in the center of the wafer and in ROM areas, these latter areas are areas that have dense polysilicon line concentrations.
FIG. 1 shows a cross section of a wafer 10 on the surface of which has been formed a number of ROM (poly) structures. A gate oxide 12 has been deposited as has a base layer 13 and a pattern 14 of polysilicon lines; spacers 15 (of for instance TEOS/SiO.sub.2) have been formed adjacent to the polysilicon lines 14. A layer 16 of BPSG has been deposited over the pattern 14 of polysilicon lines; a final layer 18 of nitride has been deposited over the poly layer. Highlighted on the surface of the poly BPSG film 16 is a grain type surface irregularity 20. These irregularities have been observed most predominantly in areas of heavy poly concentration such as the cross section shown in FIG. 1. The key point to be observed in FIG. 1 is the formation of the precipitation 20 at the surface interface of the deposited layer of BPSG. The structure as shown in FIG. 1 typically can be part of a larger device layout, this larger layout can contain an open area (no ROM structures with poly gates) as is highlighted in the following figure, that is FIG. 2.
FIG. 2 shows a cross section of an open area on the surface of wafer 10 over which a layer 22 of gate oxide and a base layer 24 is formed. A BPSG dielectric layer 26 has been deposited over the base layer 24. Highlighted on the surface of the layer of BPSG is the surface grain type irregularity 28. The area of the wafer that is shown in FIG. 2 is an open area because there is no concentration of poly structures or any other semiconductor device structures present. The key point to be observed in FIG. 2 is the formation of the precipitation 28, again (as in FIG. 1) at the surface interface of the deposited layer of BPSG.
It is understood that the two cross sections as shown in FIGS. 1 and 2 are cross sections of device features that can be contained in one and the same device. In such a layout, the ROM (poly) area and the open (no poly) area share the same layer of BPSG.
It has previously been stated that the presence of H.sub.2 O was a catalyst in forming BPSG surface irregularities. The invention teaches a method where this cause is eliminated.
U.S. Pat. No. 5,405,489 (Kim et al.) discloses a method comprising (1) deposit BPSG layer and (2) dry air/N.sub.2 treatment. The patent & discusses the B.sub.2 O.sub.2 precipitate problem.
U.S. Pat. No. 4,152,286 (Crosson et al.) shows a BSPG process.
U.S. Pat. No. 5,314,848 (Yasui et al.) shows a BSPG heat treatment, which is performed in N.sub.2.
U.S. Pat. No. 5,698,473 (Ibok et al.) teaches a BPSG process where N.sub.2 is used during heating steps.
U.S. Pat. No. 5,783,493 (Yeh et al.) shows a BPSG etchback plasma treatment.